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Verification Engineer

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Hyderabad, India

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Manual Testing

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Automotive Industry

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12/10/2026

Req. VR-125501

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Project description

This is a great opportunity to work as part of a highly regarded team to deliver leading-edge solutions.

Responsibilities
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Tests the Xilinx Vivado FPGA implementation flow itself

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placer, routing, static timing analysis

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and analyses quality of results. EDA tool QA for an FPGA engineer, not ASIC verification.

Skills

Must have

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Xilinx Vivado, specifically the implementation flow

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FPGA design flow

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static timing analysis and design constraints

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digital / logic design

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debug skills

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2-4 years of experience

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Experience: Minimum 2, maximum 4 years.

Nice to have

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EDA company experience

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scripting / automation (Tcl, Python)

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AI tool usage

Other
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Languages

English: B2 Upper Intermediate

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Seniority

Junior

Hyderabad, India

Req. VR-125501

Manual Testing

Automotive Industry

12/10/2026

Req. VR-125501

Apply for Verification Engineer in Hyderabad

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