Project description

The Principal Engineer, AI Hardware Modeling (NPU), within the NPU Hardware & Software organization, is a senior individual contributor role for an engineer with deep expertise in hardware modeling, emulation, and hardware-software co-design. This role provides expert-level technical leadership in developing and maintaining bit-accurate and cycle-accurate hardware models that represent complex AI accelerator and NPU architectures used in ADAS, autonomous driving, and in-vehicle AI platforms.
This role owns the architecture and evolution of hardware modeling frameworks, translates conceptual hardware designs into robust, scalable software models, and enables early software development, verification, and performance analysis ahead of silicon availability. The Principal Engineer, AI Hardware Modeling (NPU) operates with a high degree of autonomy, partners closely with architecture, RTL, verification, and software teams, and influences modeling methodologies across programs

Responsibilities

Hardware Model Architecture & Development (65%)

Lead the design, implementation, and maintenance of bit-accurate and cycle-accurate C/C++ hardware models representing NPU architectures and subsystems.

Model complex compute engines, memory hierarchies, interconnects, and control logic with high fidelity to hardware specifications.

Define scalable modeling architectures that evolve with changing hardware designs and microarchitecture updates.

Collaborate with architecture and RTL teams to ensure model alignment with hardware intent and implementation details.

Software Interfaces & Emulation Frameworks (15%)

Design and develop software interfaces and APIs that allow software teams to interact with hardware models as if using physical silicon.

Build emulator-style frameworks that support register-level access, memory inspection, and controlled execution of AI workloads.

Implement debugging, introspection, and tracing capabilities to support deep analysis of hardware and model behavior.

Develop integrated performance profiling and analysis tools within the modeling environment.

Verification, Validation & HW/SW Co-Design Enablement (15%)

Enable detailed inspection and modification of memory and register state to support debug, optimization, and issue triage.

Provide modeling infrastructure to support hardware-software co-verification and system-level validation.

Partner with verification teams to ensure model correctness, completeness, and alignment with verification scenarios.

Support FPGA prototyping, emulation, and early validation flows as required.

Technical Leadership & Cross-Functional Influence (5%)

Provide expert technical guidance on hardware modeling methodologies, best practices, and tooling.

Influence modeling standards and approaches across programs to improve scalability, accuracy, and developer productivity.

Communicate complex modeling concepts and limitations clearly to both technical and non-technical stakeholders.

Skills

Must have

Expert communicator across global, cross-cultural, and cross-functional teams.

Strong analytical, debugging, and system-level problem-solving skills.

Proven ability to lead complex technical initiatives without direct authority.

Quality-driven mindset with a strong focus on correctness, robustness, and coverage.

Collaborative approach across hardware, software, verification, and safety organizations.

Extensive expertise in C/C++ programming for hardware modeling and simulation.

Strong understanding of NPU or AI accelerator architectures, memory systems, and dataflow.

Solid grounding in computer architecture and digital design principles.

Experience with SystemC, transaction-level modeling (TLM), and/or hardware description languages.

Familiarity with modern software development practices, including version control, testing, and CI pipelines.

Proven experience with bit-accurate and cycle-accurate modeling and hardware-software co-design methodologies.

Proficiency in performance optimization and memory management for large-scale software systems.

Nice to have

Prior experience modeling AI accelerators, NPUs, GPUs, or similar compute architectures.

Knowledge of automotive hardware requirements and functional safety concepts.

Experience with FPGA prototyping, emulation, or hardware-in-the-loop validation.

Background in parallel computing and high-performance simulation.

Contributions to open-source modeling frameworks or relevant technical publications.

Exposure to GenAI-assisted engineering tools and AI-augmented development workflows.

Other

Languages

English: C2 Proficient

Seniority

Senior

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