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Verification Engineer
Successfully
Req. VR-121839
We are looking for a Verification Engineer to work on IP-level using a UVM-based environment. The role involves writing the test cases in UVM, performing functional Verification with RTL, and debugging issues to support timely delivery of IP
Develop and execute verification environments using Verilog/SystemVerilog with UVM-based testbenches.
Perform debug and root-cause analysis of functional failures to ensure design quality.
Verify AMBA protocols (AXI/AHB/APB) and ensure compliance with design specifications.
Contribute to SoC-level verification (including ARM-based systems, where applicable).
Create and maintain automation scripts (Perl/Tcl/Make/Shell) to improve verification efficiency and workflows.
Must have
7-10 years of experience
Good verification skills (Verilog, System Verilog)
Strong Knowledge of UVM methodology, with hands-on experience in coding testbenches and good debugging skills
AMBA
(AXI, AHB, APB)
good to have protocol knowledge
Well-versed with digital design fundamentals
Scripting
Perl, TCL, Make, Shell scripting
Nice to have
Exposure to ARM-based SOC preferred
Languages
English: B2 Upper Intermediate
Seniority
Senior
Hyderabad, IN, India
Req. VR-121839
Manual Testing
Automotive Industry
20/03/2026
Req. VR-121839
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