Senior Design Verification Engineer

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Hyderabad, IN, India

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Software - Other

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Automotive Industry

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20/02/2026

Req. VR-121137

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Project description

We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems.

At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way.

Responsibilities
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Responsible for creating a test bench for the client IP.

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Responsible for running simulation and coverage metrics for client IP

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Responsible for creating PL designs using Vivado and Vitis.

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Responsible for creating Regressions using Python scripts

Skills

Must have

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Strong proficiency in SystemVerilog and verification methodologies (UVM preferred) with 4-8 yrs experience

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Hands-on experience with QuestaSim and/or Synopsys VCS simulation environments.

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Proven experience creating testbenches, constrained-random tests, scoreboards and coverage models.

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Solid understanding of functional coverage and code coverage metrics and how to drive closure.

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Good RTL understanding (Verilog/VHDL) and ability to read and debug design source.

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A good knowledge of simulation flow

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Working experience with Vivado project flows.

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Working knowledge of Xilinx/AMD devices.

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Working experience with Linux environment.

Nice to have

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Working experience on any scripting language (TCL/Shell/Python).

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Good to have experience in Vitis flows.

Other
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Languages

English: B2 Upper Intermediate

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Seniority

Regular

Hyderabad, IN, India

Req. VR-121137

Software - Other

Automotive Industry

20/02/2026

Req. VR-121137

Apply for Senior Design Verification Engineer in Hyderabad, IN

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